65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
v dd
gnd 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
gnd
v dd 64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
gnd
gnd 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
gnd
gnd
gnd CXD2705AQ (1/2)
il08 c-mos digital audio signal processor
?op view 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80 pin
no. i/o signal pin
no. i/o signal pin
no. i/o signal pin
no. i/o signal o o o o o o o o o i i i o o o o o o gnd ea1 ea2 ea3 ea4 ea5 ea6 ea7 ea8 ta7 gnd ta6 xrst sp0 sp2 aovf redy ea0 movf sp1 o i i i i o i i i o o o o o i i o i trdt rvdt sck xlat ta5 ta4 bfot clko clki ta3 ta2 gnd ta1 ta0 soc sob soa sib sia v dd i i i i o o o o i/o i i i/o i/o i/o i/o i/o i/o i/o lrk0 lrk1 bck0 bck1 gnd d2bk d2lr d4bk d4lr tst1 gnd tst0 ed1 ed2 ed3 ed4 ed5 ed6 ed7 ed0 i/o i/o i/o i/o o o i/o i i i i i/o i/o o o o i/o ed8 ed9 gnd ed10 ed11 xoe cas ed12 ed13 td14 gnd td13 td12 ed14 ed15 xwe ras ea9 v dd td15
input
bck0, bck1
clki
lrk0, lrk1
rvdt
sck
sia,sib
ta0 - ta7
td12 - td15
tst0, tst1
xlat
xrst
output
aovf
bfot
cas
clko
d2bk
d2lr
d4bk
d4lr
ea0 - ea9
movf
ras
redy
soa-soc
sp0-sp2
trdt
xoe
xwe
input/output
ed0 - ed15 CXD2705AQ (2/2)
: bit clock
: clock
: lr clock
: data for hc i/f
: sift clock for hc i/f
: serial data
: test
: test
: test (normal ??
: mode partition signal
: reset
: alu overflow signal
: clock buffer
: column-address strobe for ext. data ram
: clock
: 1/2 bit clock
: 1/2 lr clock
: 1/4 bit clock
: 1/4 lr clock
: address for ext. data ram
: mac overflow signal
: row-address strobe for ext. data ram
: ready signal for hc i/f
: serial data
: static port 0, 1, 2
: data for hc i/f
: output enable for ext. data ram
: write enable for ext. data ram
: data input/output for ext. data ram
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